Partial-SOI high voltage laterally double-diffused MOS with a partially buried n^+-layer  

作　　者：胡盛东 武星河 朱志 金晶晶 陈银晖 

机构地区：[1]College of Communication Engineering, Chongqing University [2]National Laboratory of Analogue Integrated Circuits, No.24 Research Institute of China Electrics Technology Group Corporation

出　　处：《Chinese Physics B》2014年第6期468-472,共5页中国物理B（英文版）

基　　金：supported by the Natural Science Foundation of Chongqing Science and Technology Commission(CQ CSTC)(Grant No.cstcjjA40008);the Fundamental Research Funds for the Central Universities,China(Grant No.CDJZR12160003);the China Postdoctoral Science Foundation(Grant Nos.2012M511906 and 2013T60835);Chongqing University Postgraduates’Science and Innovation Fund,China(Grant No.CDJXS12161105)

摘　　要：A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.

关 键 词：SILICON-ON-INSULATOR breakdown voltage interface charges electric field 

分 类 号：O552.2[理学—热学与物质分子运动论]