基于MRV原理的锁相环抖动BIST电路优化与实现  

Optimization and implementation of PLL jitter BIST circuit based on MRV technique

作　　者：蔡志匡[1] 徐亮[1] 任力争 许浩博[1] 时龙兴[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《东南大学学报（自然科学版）》2014年第3期482-486,共5页Journal of Southeast University：Natural Science Edition

基　　金：国家科技重大专项资助项目(2009ZX01031);国家高技术研究发展计划(863计划)资助项目(2009AA011701);国家自然科学基金资助项目(61006029)

摘　　要：为解决传统基于游标原理锁相环片上抖动测量电路的问题,提出了一种基于多精度游标(MRV)原理的锁相环抖动内建自测试技术.该原理不仅能够大幅降低测量电路面积,同时能够有效保证测量精度,减少锁相环(PVT)的影响.将MRV原理运用在游标延时链(VDL)和游标振荡器(VRO)2种典型技术上.在VDL方案中,由单级延时链改进为两级延时链,分别采用粗细2种不同分辨率的延时单元;在VRO方案中,根据待测信号的范围,通过改变振荡器的控制信号,测量电路动态选择相应的分辨率.在TSMC 130 nm工艺下,分别对2种改进方案进行电路实现,并从分辨率、面积、测量范围、测量误差等方面进行对比分析.In order to overcome the drawbacks of PLL （phase-locked loops）on-chip jitter measure-ment circuits based on the traditional vernier principle,a novel MRV （multi-resolution vernier） BIST （built-in self-test）scheme is proposed.The principle can not only greatly reduce circuit area, but also effectively ensure the test precision and reduce the impact of PVT.MRV is applied to two typical jitter measurement circuits,namely the VDL （vernier delay line）and VRO （vernier ring os-cillator）.In the VDL scheme,the single stage delay line is improved by two level delay lines,in which fine and coarse resolution delay cells are used.In the VRO scheme,according to the scope of signals to be measured,the circuit can provide corresponding resolutions dynamically by controlling the frequency of the oscillators.Designed in TSMC 130 nm CMOS process,these two techniques are compared in terms of timing resolution,area overhead,the range of measurement and error.

关 键 词：锁相环 内建自测试 多精度游标 抖动 游标延时链 游标振荡器 

分 类 号：TN47[电子电信—微电子学与固体电子学]