一种数据Cache的设计和验证  

Design and Verification of a Kind of Data Cache

作　　者：屈凌翔[1] 袁潇[1] 王澧[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2014年第5期28-32,共5页Electronics & Packaging

摘　　要：Cache能够提高DSP处理器对外部存储器的存取速度,提高DSP的性能,设计高性能低功耗的Cache,对于提高DSP芯片的整体性能有着十分重大的意义。描述了DSP芯片中一种高性能低功耗的数据Cache。这种Cache可以通过增加具备重装功能的Line Buffer来减少处理器对Cache的访问频率,从而降低Cache功耗。通过FFT、AC3、FIR三种基准程序测试表明,Line Buffer可以降低35%的Cache访问频率,明显降低了数据Cache功耗。Cache can speed up the access to memory from DSP processor and enhance DSP performance at the same time. Thus, to enhance the performance of the whole DSP processor, it is of great signiifcance to design a kind of cache that is of high performance and low power. The thesis describes the system architecture of data cache and function simulation of the cache. This kind of cache contains a line buffer to reduce the access frequency from the CPU to cache, so as to decrease the power consumption. By running three benchmarks including FFT AC3 and FIR, made a conclusion that the line buffer reduces the access frequency from DSP core to cache by 35%, obviously decreases power consumption of the data cache.

关 键 词：数据CACHE 重装控制 LINE BUFFER 

分 类 号：TN402[电子电信—微电子学与固体电子学]