基于FPGA的高速导航解算硬件实现  

The hardware implementation of a navigation solution system based on FPGA

作　　者：沈继睿[1] 郑永安[1] 史忠科[1] 

机构地区：[1]西北工业大学自动化学院,陕西西安710129

出　　处：《电子设计工程》2014年第11期103-106,共4页Electronic Design Engineering

基　　金：国家自然科学基金重点项目(61134004)

摘　　要：针对现有小型无人机导航系统的解算速度慢、多处理器核心臃肿可靠性差的缺点,实现了一种仅使用单一FPGA作为数据处理核心的小型高速导航解算系统。该系统对飞机运动方程组和导航方程组进行并行化分解,对相互独立的中间变量进行并行计算,使得单个运算周期能够同时进行6次浮点运算,在不盲目增加硬件消耗的条件下有效提高了解算速度。仿真和实验结果表明系统能够高效地进行导航信息解算,在小型无人机的导航控制领域有重要的工程应用价值。In view of the defect of bloat hardware, poor operational reliability, and low process speed of existing embedded navigation system, this paper proposes a navigation solution system based on a single FPGA chip. The vehicle motion equations and the navigation equations are parallel decomposed by the system and parallel computation was carried out on the independent variables. Six times of floating-point calculation are made in a cycle which makes the calculating speed increased while the hardware resources consumption does not occupied too much. The simulations and experiments indicate that the system works well and it has important value in the field of navigation of small UAV.

关 键 词：并行计算 FPGA 姿态解算 导航解算 

分 类 号：TN06[电子电信—物理电子学]