卫星导航抗干扰专用芯片后端版图设计  

Bankend Layout Design of Anti-Jamming Performance of Satellite Navigation System ASIC Chip

作　　者：张文华[1] 

机构地区：[1]中国电子科技集团公司第二十研究所,西安710068

出　　处：《现代导航》2014年第3期183-186,共4页Modern Navigation

摘　　要：随着电磁环境的日益复杂,卫星导航接收系统的抗干扰性能要求越来越高。在小型卫导接收系统的抗干扰设计中,体积和功耗已经成为最大的限制因素,抗干扰芯片的设计已成为解决该问题的有效途径。本文基于SoC Encounter后端版图设计工具,通过布局规划、电源设计、标准单元放置、时钟树综合及优化、布线等后端版图设计流程,完成了一款卫星导航抗干扰专用芯片的后端版图设计工作。With the electromagnetic environment getting more complicate,the anti-jamming performance of satellite navigation system is becoming more and more strictly. In those small Satellite Navigation products, power and size are the two most important limiting factors. An anti-jamming performance of satellite navigation system ASIC chip could solve this problem effectively. The bank-end layout design about this anti-jamming satellite navigation ASIC chip is proposed in this paper. In the design process, floorplan, place, route, stationary timing analysis and optimizing are introduced based on SOC Encounter bank-end layout design tool.

关 键 词：卫星导航 专用芯片 后端版图设计 SOC ENCOUNTER 

分 类 号：TN966[电子电信—信号与信息处理]