CMOS可预置双边沿触发器的设计及其应用  

Design of CMOS Pre-settable Double-edge-triggered Flip-flop and Its Application

作　　者：吴训威[1] 卢仰坚[2] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211 [2]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《电路与系统学报》2001年第1期27-31,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金!(No.69773034);浙江省自然科学基金!(No. 697064)

摘　　要：本文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出一种基于CMOS传输门的双边沿触发器设计，并设置了它的直接预置控制端以使达到实用的要求。该触发器已用PSPICE程序模拟验证了具有完整的功能。使用该触发器设计时序系统的实例被演示。对模拟所得数据的计算结果表明，与采用相同功能的单边沿触发器的系统比较，由于工作频率减半可使采用双边沿触发器的系统功耗明显降低。To erase the bootless power dissipation of the redundant transition of the clock，a design method named DET (double-edge-triggered) flip-flop using CMOS transmission gate is proposed. The directly pre-set terminals are increased in the design to meet the requirement for practical application. This DET flip-flop is proved having a complete logic function shown by PSPICE simulation. A practical sequential system designed with the DET flip-flop is demonstrated. Calculation for the data resulted from simulation shows that power dissipation of the system adopting DET flip-flop can be reduced evidently because of using the clock with half working frequency，in comparison with its counterpart adopting SET flip-flop.

关 键 词：逻辑设计 集成电路 CMOS 预置 双连沿触发器 设计 

分 类 号：TN783[电子电信—电路与系统]