一种在VLSI电路物理设计中减小串扰的优化算法  

An Optimization Algorithm for Minimizing Crosstalk in VLSI Circuit's Physical Design

作　　者：张徐亮[1] 赵梅[2] 范明钰[3] 李春辉[3] 虞厥邦[3] 黄劲 

机构地区：[1]电子科技大学信息中心,成都610054 [2]中国科学技术大学研究生院计算机科学系,北京100039 [3]电子科技大学光电子技术系,成都610054 [4]AmbowCorporation,2701NorthWesternParkway

出　　处：《计算机辅助设计与图形学学报》2001年第4期289-293,共5页Journal of Computer-Aided Design & Computer Graphics

基　　金：中国博士后基金和;川省科技厅应用基础研究专项经费资助

摘　　要：通过研究调整线段和线间距对串扰的影响 ,提出了一种在布线时通过采取作线段摄动和压缩线间距的措施来减小串扰的优化算法 .计算机仿真结果表明 ,该算法能有效地减少芯片中的串扰 .此外 。One of major concerns in physical design of deep submicron VLSI circuits is to minimize the influence of crosstalk which will affect the chip's performance significantly if the designer does not pay attention to it in the phase of detailed routing. By studying how crosstalk is varying when adjusting wire's segment and space between neighboring wires, an optimization algorithm aimed at minimizing crosstalks by wire perturbation and space compression is developed in this paper. Computer simulation results show that the algorithm is effective in significantly decreasing chip's crosstalk. It is expected that the algorithm is applicable in the case of irregular routing areas.

关 键 词：超大规模集成电路 物理设计 串扰最小化 优化算法 VLSI 计算机仿真 

分 类 号：TN470.2[电子电信—微电子学与固体电子学]