微处理器段高速缓存器加载算法及设计  

Design of microprocessor segment cache loading

作　　者：李树国[1] 周润德[1] 羊性滋[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《清华大学学报（自然科学版）》2001年第7期102-105,共4页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金资助项目 (5 9995 5 5 0 -1);清华大学"九八五"项目

摘　　要：段高速缓存器加载是微处理器保护方式下多任务调度、虚拟段式存储器管理及指令集使用频度较高的部分。文中探讨了段高速缓存器加载的数据结构和定义 ,给出了保护方式下段高速缓存器加载算法 ,提出了用于段高速缓存器加载的保护测试单元的细胞群结构。最后 ,用 EDA工具SYNOPSYS对段高速缓存器加载算法的微程序和段高速缓存器加载的保护测试单元 RTL级的 VHDL描述进行了综合与仿真 。In microprocessor protected mode, the segment register does not represent the segment base address as in real mode but becomes a selector which can index a descriptor in the GDT/LDT (Global/Local descriptor table). A descriptor contains a segment base address, a limit and an attribute. The number of visits to descriptors in memory can be reduced by having every segment register set up a corresponding segment cache to hold a descriptor. This paper firstly analyzes the definitions and data structures for segment cache loading to design an algorithm for segment cache looding. The algorithm is then used to propose a kind of cell group architecture to build the PTU (Protection Test Unit) for segment cache loading. A boolean value is generated from the PTU to control branching of the microprogram for the segment cache loading algorithms. The RTL VHDL description for the PTU and the microprogram have been synthesized for the algorithm with SYNOPSYS tools to prove the validity of the PTU.

关 键 词：段高速缓存器 细胞群结构 保护测试单元 微处理器 加载算法 数据结构 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]