一种新的CMOS电路最大功耗估计方法  

A NOVEL ATPG APPROACH TO MAXIMUM POWER ESTIMATION OF CMOS CIRCUITS

作　　者：骆祖莹[1] 闵应骅[2] 杨士元[1] 

机构地区：[1]清华大学自动化系,北京100084 [2]中国科学院计算技术研究所信息网络研究室,北京100080

出　　处：《计算机研究与发展》2001年第12期1418-1422,共5页Journal of Computer Research and Development

基　　金：国家自然科学基金重点项目基金资助 ( 6 97330 10 )

摘　　要：过大的峰值功耗会使芯片承受过大的瞬间电流冲击 ,降低芯片的可靠性及性能 ,因此有效地对电路最大功耗作出精确的估计非常重要 .为了在尽可能短的时间内对 VL SI电路的最大功耗下限作出较为可信的估计 ,给出了一种新的 CMOS电路最大功耗估计方法 .ISCAS85电路集的实验结果表明这种估计方法不仅对于无时间延迟功耗计算模型 ,而且对于有时间延迟功耗计算模型 ,都具有最大功耗估计值较准确和耗时短的优点 .High peak power makes power distribution network suffer from great instantaneous current and severe electro-migration, resulting in lower chip's reliability and performance. Thus, it's very important to effectively estimate an accurate peak power dissipation of a circuit. In order to obtain an efficient estimation of least bound of the peak dissipation of a VLSI chip, a novel approach is proposed in this paper. Experiments with the ISCAS85 benchmarks demonstrate that this approach is time-saving and can give more accurate estimation of peak power not only for the delay-free model, but also for the delay model of maximum power of CMOS circuits.

关 键 词：ATPG 最大功耗估计 CMOS电路 集成电路 VLSI 

分 类 号：TN432[电子电信—微电子学与固体电子学]