数字逻辑电路的描述及模块化综合方法  

Description of the Digital Logic Circuit and Method of Model Synthesis

作　　者：钱培怡[1] 于德泳[1] 

机构地区：[1]抚顺石油学院信息工程分院,辽宁抚顺113001

出　　处：《系统工程与电子技术》2002年第3期16-18,共3页Systems Engineering and Electronics

摘　　要：随着电子设计自动化技术的进步 ,大多数现代数字电路或系统的设计工程都离不开计算机辅助设计(CAD)工具的帮助 ,尤其是出现了高级语言描述、系统仿真和综合技术为特征的第三代EDA技术。因此掌握好数字逻辑电路或系统的描述 (建模 )方法和综合步骤是至关重要的。介绍了高级描述语言VHDL的行为描述和结构描述的若干种模型 。As the progress of the electronic design automation technique, especially the 3th generation of the EDA technique with the features of the nigh Language, system simulation and synthesis technique come into being, most modern digital circuit or system require the help by the computer aid design. Hence, it is very important to master the description (modeling) methods and steps for synthesis. The paper introduces some models of the description for behavioral and structure with VHDL language. By one design example the synthesis from definition to realization have been provided which illustrates the design cycle for digital logic circuit.

关 键 词：数字逻辑电路 描述 HDL语言 模块化 

分 类 号：TN791[电子电信—电路与系统]