衬底电压自举结构的10位120 MS/s SAR ADC  

A 10 bit 120 MS/s SAR ADC Based on Substrate Voltage Boost Structure

作　　者：陈光炳[1] 徐代果[1] 李曦 CHEN Guangbing;XU Daiguo;LI Xi(Science and Technology on Analog Integrated Circuit Laboratory,Chongqing 400060,P.R.China;Sichuan Institute of Solid-State Circuits,China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)

机构地区：[1]模拟集成电路国家重点实验室,重庆400060 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2018年第6期722-727,共6页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(0C09YJTJ1603)

摘　　要：基于采样管衬底电压自举结构,提出了一种高线性低阻抗采样开关技术。在保证采样开关等效输入阻抗较小的同时,实现了采样开关的源/漏极与衬底之间的寄生电容不随输入信号幅度的变化而变化;减小了动态比较器输入管的等效导通电阻,提高了动态比较器输入管的跨导,解决了动态比较器的速度与噪声折中的难题。基于65nm CMOS工艺,设计了一种10位120MS/s SAR ADC。在1V电源电压下,功耗为1.2mW,信号噪声失真比SNDR>55dB,无杂散动态范围SFDR> 68dB,在奈奎斯特采样情况下,优值(FoM)为22fJ/(conv·step)。Based on substrate voltage boost technique,a high linearity and low resistarice sampling switch technique was proposed.With a lower on-resistance,the parasitic capacitances of source/drain to substrate were independent with the change of input signal.Further,the input pair's on-resistance of dynamic eomparator was reduced.The input pair's transconductance of dynamic comparator was increased.Thereby,the trade-off between speed and noise in the design of comparator was relaxed.A design example of 10bit 120MS/s SAR ADC was fabricated in a 65-nm CMOS technology,consuming 1.2.mW at a 1V power supply.It achieved a SNDR>55dB and SFDR>68dB.The corresponding figure-of-merit (FoM)was 22fJ/(conv·step)at Nyquist rate.

关 键 词：衬底电压自举 高线性低阻抗开关 高速低噪声比较器 

分 类 号：TN792[电子电信—电路与系统]