高压大功率芯片封装的散热研究与优化设计  

Thermal Research and Optimization Design of High Voltage and High Power Chip Package

作　　者：王德成 杨勋勇 杨发顺[2] 胡锐 王志宽[3] 陈潇 WANG Decheng;YANG Xunyong;YANG Fashun;HU Rui;WANG Zhikuan;CHEN Xiao(Guizhou Zhenhua Fengguang Semiconductor Co.,Ltd.,Guiyang 550018,P.R.China;Department of Electronic Science,Guizhou University,Guiyang 550025,P.R.China;Sichuan Institute of Solid-State Circuits,China Elec.Technol.Group Corp.,Chongqing 400060,P.R.China)

机构地区：[1]贵州振华风光半导体有限公司,贵阳550018 [2]贵州大学电子科学系,贵阳550025 [3]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2018年第6期850-854,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61464002);贵州省重大科技专项(黔科合重大专项字[2015]6006);贵州省科学技术基金资助项目(黔科合[2014]2066号);贵州省功率元器件可靠性重点实验室开放基金资助项目(KFJJ201504)

摘　　要：针对单片高压功率集成电路芯片,利用Flo THERM软件,建立三维结构的封装模型,并对各模型进行了仿真。研究了在不同基片材料、不同粘结层材料、不同封装外壳条件下封装模型的温度变化情况,分析得出一个最优的封装方案。结果表明,当基片材料采用BeO陶瓷、粘结层采用AuSn20合金焊料、封装外壳采用金属Cu时,该封装模型的温度最低、散热效率最高。Three-dimensional packaging models for monolithic high voltage power IC chips were built on Flo THERM software and each proposed model was simulated.Temperature variation of different models with different substrate materials,different adhesive layer materials and different packaging shells had been studied,and an optimized package scheme was given based on the analysis.Results showed that with substrate material of BeO ceramic,bonding layer of AuSn20 alloy solder,and package shell of TO-3,the temperature of the package was the lowest,and this packaging scheme had the highest efficiency of heat dissipation.

关 键 词：三维封装模型 单片型高压功率芯片 散热效率 

分 类 号：TN407[电子电信—微电子学与固体电子学]