双极IC用双埋层图形衬底制备N/P异型硅外延结构  

N/P Heterogeneous Silicon Epitaxial Structure Deposited on the Pattern Substrate of Bipolar IC with Double-buried Layer Graphics

作　　者：李明达[1] 李普生[1] LI Mingda;LI Pusheng(The 46th Research Institute,China Electronic Technology Group Company,Tianjin,300220,CHN)

机构地区：[1]中国电子科技集团公司第四十六研究所,天津300220

出　　处：《固体电子学研究与进展》2018年第6期456-464,共9页Research & Progress of SSE

摘　　要：利用PE2061s型常压桶式多片外延炉,在P型双埋层图形硅衬底上沉积生长高均匀性低缺陷的N型外延层。通过研发衬底背面杂质掩蔽、附面层虹吸效应、高补偿缓冲层生长等技术,使外延层图形漂移率、图形畸变率、均匀性以及表面质量等关键指标明显改善,最终制备出图形漂移率72%,图形标记长宽比保持为1∶1,电阻率的片内不均匀性<1.5%,片间不均匀性<2%,表面无亮点、凹坑和雾迹等缺陷的埋层硅外延片。采用该外延片制备的双极IC芯片经测试满足各项电参数指标要求,表明常规埋层关键工艺取得了关键突破,可以满足工程化批产要求。Using PE2061 satmospheric pressure barrel-type multi-wafer epitaxial furnace,high-uniformity and low-defect N-type epitaxial layer was deposited on the P-type double buried layer patterned silicon substrate.The impurity on the reverse of the substrate closed,the boundary layer siphon effect,high compensation buffer layer growth and other methods were successfully achieved,the pattern drift rate,pattern distortion,uniformity and surface quality of the epitaxial layer were significantly improved.Finally,buried silicon epitaxial wafer has been prepared with pattern drift of only 72%,pattern mark aspect ratio remaining of 1∶1,resistivity parameter nonuniformity within wafer of less than 1.5%,wafer nonuniformity of less than 2%,and no defects such as bright point,dimples and haze marks on the surface.The bipolar IC chip prepared by the epitaxial wafer has been tested to meet the requirements of various electrical parameters,indicating that the key process of the conventional buried layer has achieved a key breakthrough and can meet the requirements of engineering batch production.

关 键 词：埋层外延 图形漂移 图形畸变 缓冲层 

分 类 号：TN304.054[电子电信—物理电子学]