一种高精度锁相环抖动测量电路设计  

Design of high precision jitter measurement circuit ofphase locked loop

作　　者：蔡志匡[1,2] 王昌强 王子轩 代鸣扬[1] 肖建 CAI Zhikuang;WANG Changqiang;WANG Zixuan;DAI Mingyang;XIAO Jian(College of Electronic and Optical Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,China;School of Biological Sciences and Medical Engineering,Southeast University,Nanjing 210096,China)

机构地区：[1]南京邮电大学电子与光学工程学院,江苏南京210023 [2]东南大学生物科学与医学工程学院,江苏南京210096

出　　处：《南京邮电大学学报（自然科学版）》2018年第6期29-35,共7页Journal of Nanjing University of Posts and Telecommunications：Natural Science Edition

基　　金：国家自然科学基金(61504065;61504061;61501261);江苏省自然科学基金(BK20150848);南京邮电大学引进人才科研启动基金(NY214157)资助项目

摘　　要：锁相环作为数字和模拟电路中不可或缺的基本电路单元,其性能的稳定性在电路工作过程中尤为重要。基于欠采样的抖动测量电路是目前锁相环片上测试领域的研究热点。文中针对目前抖动测量方案存在的测量精度低和测量成分单一的问题,基于欠采样测量原理,设计了一种高精度锁相环抖动测量电路,能够实现周期抖动和长周期抖动的测量。在SMIC 40 nm LL工艺条件下,完成前后仿真:针对多组测试数据,得出周期抖动测量平均误差是2. 81%,长周期抖动测量的平均误差是3. 67%,电路面积为2 448μm2,功耗为0. 37 m W,满足设计需求。The phase locked loop(PLL) is an indispensable basic circuit in analog and digital communication systems and the stability of performance is particularly important in the circuit work process. Theundersampling-based jitter measurement circuit is currently a research focus in the field of phase-lockedloop testing. This paper presents a jitter extraction technique based on edge alignment on the low accuracyand large measurement error of the existing jitter extraction methods for undersampling circuits,the idea ofedge alignment is applied to the measurement of periodic and long-period jitters. The simulation results onSMIC 40 nm LL show that the average error of the periodic jitter measurement is 2. 81% and the averageerror of the long-period jitter measurement is 3. 67%,the circuit area is 2 448 μm2,and the power consumption is 0. 37 m W,thus meeting the design requirements.

关 键 词：高精度 边沿对齐 周期抖动测量 长周期抖动测量 欠采样 

分 类 号：TN919.8[电子电信—通信与信息系统]