基于Booth编码模乘模块RSA的VLSI设计  

VLSI implementation of RSA cryptosystem based on the Booth-encoded montgomery module

作　　者：舒妍[1] 卢君明[2] 

机构地区：[1]西安电子科技大学机电工程学院,陕西西安710071 [2]上海交通大学大规模集成电路研究所,上海200030

出　　处：《西安电子科技大学学报》2002年第3期363-367,共5页Journal of Xidian University

摘　　要：在Montgomery模乘算法基础上 ,采用大数乘法器常用的Booth编码技术缩减Montgomery模乘法的中间运算过程 ,将算法迭代次数减为原来的一半 .同时采用省进位加法器作为大数加法的核心 ,使模乘算法中一次迭代的延迟为两个一位全加器的延迟 ,提高了处理器的时钟频率 .在 0 2 5 μm工艺下 ,对于10 2 4位操作数 ,可在 2 0 0MHz时钟频率下工作 ,其加密速率约为 178kbit/s .The RSA public key crypto-system is a relatively safe technology, which is widely used in today's secure electronic communication. The RSA algorithm is a modular exponentiation algorithm and its core operation is modular multiplication. In this paper, the Booth-encoded technique that is commonly used in large integer multiplication is merged into the Montgomery modular multiplication algorithm. Using this algorithm, iteration number is reduced to about n/ 2 in each Montgomery operation. In addition, the carry saving adder is used as the core of the large integer addition and the delay of the iteration in modular multiplication is equated to the delay of two one-bit full adders. At a clock of 200?MHz, the encryption rate is about 178?kbit/s for 1?024-bit operands.

关 键 词：BOOTH编码 模乘模块 RSA VLSI设计 模幂乘法 模乘算法 因特网 安全 

分 类 号：TP393.08[自动化与计算机技术—计算机应用技术]