RTL综合中VHDL算术操作符的综合  

VHDL Arithmetic Operator Synthesis in RTL Synthesis

作　　者：谢巍[1] 袁媛[1] 刘昕宇 刘明业[1] 

机构地区：[1]北京理工大学ASIC研究所,北京100081

出　　处：《计算机辅助设计与图形学学报》2002年第8期727-730,734,共5页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金 ( 6 99730 0 7)资助

摘　　要：寄存器传输级 (RTL)综合实现从 RTL 行为描述到门级结构描述的转换 ,是目前 EDA设计行业的主流设计方法 .算术操作符是 RTL综合中难于综合的一类操作符 ,文中详尽解释了 IEEE制定的有关算术操作符的各种限制 ,并对部分算术操作符的限制阐述了自己的观点 ;分析了各算术操作符的实现方案 ,并基于电路面积、电路速度 ,确定了适合 RTL综合的实现方案 ;最后 ,给出在自行开发的 RTL综合工具中进行的算术操作符综合测试 ,测试表明 。As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain. Arithmetic operator is a kind of operators which is very difficult to synthesize in RTL synthesis. In this paper, we analyze all restrictions on arithmetic operators set by IEEE, and set forward our viewpoint on some arithmetic operators. In addition, we give forth implement solutions for each arithmetic operator and underline those solutions which suit RTL synthesis. Finally, the paper presents tests done on the RTL synthesis tool developed by the authors, which show that these implement solutions are feasible and effective.

关 键 词：RTL综合 VHDL语言 算术操作符 专用集成电路 

分 类 号：TN492[电子电信—微电子学与固体电子学]