基于FPGA的FIR数字滤波器设计与仿真  

Design and Simulation of FIR Digital Filter Based on FPGA

作　　者：叶亚东 蔺智挺[1] 范玉红[1] 

机构地区：[1]安徽大学电子信息工程学院,安徽合肥230601

出　　处：《电子科技》2014年第7期67-70,共4页Electronic Science and Technology

基　　金：国家科技重大专项课题基金资助项目(2011ZX01034-001-002-003);安徽省自然科学基金资助项目(KJ2013A006)

摘　　要：采用改进并行分布式算法设计了一种16抽头FIR数字低通滤波器,首先用Matlab工具箱中的FDATool设计滤波器系数,然后使用硬件描述语言Verilog HDL和原理图,实现了子模块和系统模块设计,在Matlab与QuartusII中对系统模块进行联合仿真。仿真结果表明,设计系统性能稳定,滤波效果良好,且实用性较强。A 16 taps FIR digital low-pass filter is designed, whose performance is improved by parallel distributed arithmetic. The FDATool of Matlab is used to design the filter coefficients. The sub module and system module are designed with Verilog HDL and Block Diagram respectively. Simulation with Matlab and QuartusII show that the designed system has stable performance, good effect and strong applicability.

关 键 词：分布式算法 FDATool VERILOG HDL QuartusⅡ 

分 类 号：TN713.7[电子电信—电路与系统]