一种新型的FPGA配置位流压缩算法  

A Novel Bitstream Compression Method for FPGA

作　　者：王驰[1] 王健[1] 杨萌[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2014年第3期365-370,共6页Journal of Fudan University：Natural Science

基　　金：国家高技术研究发展计划(2012AA012001)资助项目

摘　　要：针对FPGA位流存储空间和下载时间日益增大的问题，提出了一种新型的位流压缩算法．该算法利用位流中存在的局部稀疏特性，对出现频次较高的少1符号进行压缩编码．本文围绕Virtex-4系列FPGA位流展开实验，分析了该算法中不同参数取值对压缩效率的影响，发现符号长度（Ls）及压缩阈值（T）合适的选值能够获得较为理想的结果．本文所提算法与另外一种实用的位流压缩算法LZSS相比压缩比减小了8％～12％．此外，本文算法相应的解压缩算法也十分简单，易于用硬件实现．In order to reduce the continuously increasing memory cost and downloading time overhead of FPGA bitstream, a novel bitstream compression method is proposed. Based on the local and sparse bit distribution existing in bitstream, our method encodes symbols that have fewer 1-bits with high frequency. We have experimented on the Virtex-4 bitstream and analyzed the impact made by symbol length and compression threshold and find that the algorithm may have optimal results given proper selections. Compared to LZSS, another practical bitstream compression method, the simulation results demonstrate that our method can achieve compression ratios 8%--12% better than that of LZSS. Moreover, our compression method is easy to implement with hardware.

关 键 词：现场可编程门列阵 配置位流 符号维度压缩 

分 类 号：TN402[电子电信—微电子学与固体电子学]