纳米尺度超低漏电ESD电源钳位电路研究  

Novel Ultra-Low-Leakage ESD Power Clamp Circuit in Nanoscale Process

作　　者：王源[1] 张雪琳[1] 曹健[1] 陆光易[1] 贾嵩[1] 张钢刚[1] 

机构地区：[1]北京大学微电子学研究院、教育部微电子器件与电路重点实验室,北京100871

出　　处：《北京大学学报（自然科学版）》2014年第4期595-599,共5页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：国家重点基础研究发展计划(2011CBA00606);国家自然科学基金青年基金(61106101)资助

摘　　要：提出一种新型超低漏电ESD电源钳位电路。该电路采用具有反馈回路的ESD瞬态检测电路,能够减小MOS电容栅极–衬底之间电压差,降低电路的泄漏电流,抑制ESD泄放器件的亚阈值电流。65 nm CMOS工艺仿真结果表明,在电路正常上电时,泄漏电流只有24.13 nA,比传统ESD电源钳位电路的5.42μA降低两个数量级。A novel electrostatic discharge （ESD） power clamp circuit with ultra-low leakage current is proposed. An ESD transient detective circuit with feedback loop is used to reduce the voltage between the bulk and gate of MOS capacitor, which results in a ultra-low leakage current performance of novel circuit. Verified by HSPICE simulation in 65 nm CMOS process, the standby leakage current of novel circuit is 24.13 hA, which is more than two-orders lower than that of the traditional design about 5.42 μA.

关 键 词：静电放电 泄漏电流 电源钳位电路 亚阈值电流 

分 类 号：TN86[电子电信—信息与通信工程]