基于FPGA的时间数字转换电路设计与测试  

Design and Testing of Time-to-digital Convertor Based on FPGA

作　　者：张云雷[1,2] 张珂殊[1] 邵永社[1] 孟柘[1] 

机构地区：[1]中国科学院光电研究院,北京100094 [2]中国科学院大学,北京100049

出　　处：《计算机技术与发展》2014年第8期175-178,共4页Computer Technology and Development

基　　金：国家科技支撑计划项目(2012BAH34B01);国家自然科学基金资助项目(61205161)

摘　　要：为满足激光雷达系统多通道、精确处理大量时间数据的需求,利用抽头延时线技术,在Virtex6 FPGA上采用Verilog语言实现了时间数字转换电路(Time-to-Digital Convertor,TDC)。文中在领域分析的基础上明确了时间数字转换电路的主要原理,对电路的各模块进行详细设计,并通过GPX测试芯片与在FPGA内部实现的TDC电路进行实时对比测试,修正系统固定误差。实验表明,该课题设计的多通道TDC电路各通道间的测量误差在1 LSB左右,每个通道测量分辨率可达58 ps。采用GPX芯片进行校准测试的方案排除了信号源误差,优于传统检校方案。In order to meet the requirement of LiDAR （ Light Detection And Ranging） system in measuring precise time with multiple channels,a Time-to-Digital Convertor （ TDC） using tapped delay line technology is implemented with Verilog HDL upon Virtex6 FPGA. The main principle of TDC is clarified based on domain analysis,and then each module of the circuit is designed in detail. Furthermore,the fixed error of the designed TDC is calibrated with the more precise GPX timing chip. Experimental data shows that not only an accuracy of 1 LSB is achieved in all 48 channels,but also the time resolution of a single channel is improved to 58 ps. The calibration scheme adopting the GPX chip has eliminated the error of the signal source, which is consequently more reliable than the traditional scheme.

关 键 词：激光测距 时间数字转换 延时线 可编程逻辑器件 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]