定点小数乘法器的低功耗算法与实现技术  

Low power methodology and implementation for fixed-point decimal multiplier

作　　者：袁博[1] 刘红侠[1] 

机构地区：[1]西安电子科技大学微电子学院宽禁带半导体材料与器件国家重点实验室,陕西西安710071

出　　处：《中南大学学报（自然科学版）》2014年第1期132-141,共10页Journal of Central South University:Science and Technology

基　　金：国家自然科学基金资助项目(60976068);教育部科技创新工程重大项目培育资金资助项目(708083);教育部博士点基金资助项目(200807010010)

摘　　要：针对集成电路前端设计中的定点小数乘法器,提出一种既能够优化其内部加法器数量又能优化各级加法结果位宽的低功耗算法,而且在算法的实现技术上,解决目前低功耗设计中算法自身逻辑单元引入被优化系统从而降低系统优化效果的问题。在介绍该算法的理论基础和实现细节后,为了取得更加客观、更具有统计特性的低功耗优化效果,以该算法对某含有大量不同类型小数乘法器的射频模块进行优化。优化后FPGA测试结果显示逻辑占用率降低了39.3%,寄存器总数降低了45.0%,内存占用率降低了36.9%。该算法是一种高效的低功耗算法,并且解决了一般算法实现技术的缺陷与不足,其适用于对含有大量小数乘法运算的系统进行低功耗优化,例如数字信号处理和数字滤波器等。A low power methodology for fixed-point decimal multiplier in IC design was presented to optimize the number and width of the adders that were inside of synthesized multiplier. In terms of methodology implementation, it resolved the problem of optimization logic joining into optimized system, which existed in present low power design. The theoretical basis and the design method were explained. In order to get more objective and statistical test result, the methodology and implementation were used to optimize a radio-frequency module. FPGA test results show that logic utilization is reduced by 39.3%, the total number of registers used is reduced by 45.0%, and the total block memory bits utilization is reduced by 36.9%. These results show that the proposed low-power design is an effective method, which has good performance on optimizing the system including large-scale decimal multipliers, such as DSP and digital filter.

关 键 词：定点小数乘法 加法器数量 位宽 缺省 逻辑单元 功耗 面积 

分 类 号：TN702[电子电信—电路与系统] TN402