SiC材料的ICP-RIE浅槽刻蚀工艺  

Technology of SiC Shallow Groove Etching by ICP-RIE

作　　者：闫锐[1] 李亮[1] 默江辉[1] 崔玉兴[1] 付兴昌[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2014年第8期600-604,共5页Semiconductor Technology

摘　　要：介绍了用于SiC器件浅槽制作的ICP-RIE刻蚀原理,选用Cl2/Ar混合气体对SiC材料进行浅槽刻蚀,研究了ICP功率和RIE功率对刻蚀速率、刻蚀后表面粗糙度及刻蚀倾角的影响,得到了刻蚀速率、刻蚀后表面粗糙度及刻蚀倾角随刻蚀功率的变化规律。最终得到了用于SiC器件浅槽刻蚀的最优刻蚀条件。实验结果表明,RIE功率和ICP最优功率配比分别为12和500 W。该刻蚀条件应用于SiC MESFET制备中,进行了多凹槽栅结构的浅槽刻蚀,实现了多凹槽栅结构。不同深度栅凹槽的片内均匀性均达到了4%以内,片间均匀性也达到了5%,工艺稳定性及均匀性均达到了批量生产要求。The ICP-RIE etching principle of SiC device shallow groove was introduced. The C12/Ar mixture was used to etch shallow groove on SiC material and the influences of the ICP power and RIE power on the etching rate, surface roughness, etching slope were evaluated. The etching power change regulation and the etching rate, surface roughness, etching slope and uniformity were obtained. Finally, the optimal shallow groove etching condition of SiC devices was taken to get the ICP-RIE technology. Experimental results show that the 12 W of RIE power and 500 W of ICP power can get a good balance of all the result parameters. The shallow groove etching process was used in SiC MESFET fabrication to realize the multiple recess gate structure. The result shows a good multiple recess gate structure is obtained. The different depths of a gate groove on-chip uniformity are achieved within 4%, batch uniformity also is 5%. The manufacture requires of the stability and uniformity in process were satisfied.

关 键 词：SiC ICP-RIE 浅槽刻蚀 表面粗糙度 刻蚀倾角 

分 类 号：TN305.7[电子电信—物理电子学]