面向内存的混合容错编码动态调节设计  

A Dynamic Adjustment Design for Hybrid Fault-tolerant Code in Memory System

作　　者：李冰[1,2,3] 单书畅[1,2] 胡瑜[1,2] 高翔[1,2,3] 李晓维[1,2] 

机构地区：[1]计算机体系结构国家重点实验室,北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院大学,北京100049

出　　处：《计算机辅助设计与图形学学报》2014年第9期1479-1486,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金项目(61076018;61274030);国家"九七三"重点基础研究计划基金项目(2011CB302503);中国科学院计算技术研究所-华为联合实验室项目(YBCB2011030)

摘　　要：针对内存系统中高强度的容错编码容易造成过大开销的问题,为同时实现容错强度和容错开销的权衡,提出一种低开销的支持混合容错编码的动态调节设计.通过分析发现常见纠错检错编码数据位长与校验位长存在固定的比例关系,提出一种地址映射逻辑电路;当系统存取内存数据及容错强度发生调节时,该方法可保证容错编码中校验信息的存取,实现对内存容错强度调节以及数据与校验信息在内存中分开存储的支持.实验结果表明,文中设计简单,硬件和性能代价小、功耗开销低.An address mapping design which supports the adjustment of hybrid ECC codes is proposed to achieve tradeof{ between reliability and cost. We have observed that a proportional relationship exists between the length of data and the length of the check information for ECC codes, so we propose an address mapping logic. Since the data and the check information are separately stored, once the memory is accessed or the fault tolerance level is changed, the address mapping logic is able to guarantee the accesses to the check information, and to facilitate the adjustment of the fault tolerance level. The experimental results indicated that this method is effective with negligible performance and power cost.

关 键 词：内存系统 可靠性 容错设计 纠错检错编码 

分 类 号：TP306.2[自动化与计算机技术—计算机系统结构]