Intel SoC处理器的I^2C总线IP核设计与应用  

Design and Application of I^2C Bus IP Core Based on Intel SoC

作　　者：江寅[1] 杨斌[1] 

机构地区：[1]西南交通大学信息科学与技术学院,成都610031

出　　处：《单片机与嵌入式系统应用》2014年第9期24-27,共4页Microcontrollers & Embedded Systems

摘　　要：Intel SoC处理器E6x5C系列产品,作为多芯片的封装芯片,具有出色的灵活性。本文基于该处理器,利用Altera新一代集成开发工具Qsys,描述了I2 C总线IP核的设计过程,给出了IP核的系统接口和各个子模块的设计方法,并进行仿真和验证,最后将该IP核应用于模拟视频解码芯片SAA7113的配置及初始化。As multi-chip package chips,Intel SoC processor E6x5C series have excellent flexibility Based on the processors, this paper uses Altera＇s new integrated development tool called Qsys to describes the design process of I^2C bus IP core. The design methods of various submodules and system interfaces of IP core are given,and the emulation and verification are completed. Finally,the IP core is used in the configurition and initializion of analog video decoder chip SAA7113.

关 键 词：片上系统 Qsys E6X5C I^2C总线 SAA7113 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]