一位可重构三值光学处理器的设计和实现  

Design and Implementation of a 1-bit Reconfigurable Ternary Optical Processor

作　　者：王宏健[1] 金翊[1] 欧阳山[1] 

机构地区：[1]上海大学计算机工程与科学学院,上海200072

出　　处：《计算机学报》2014年第7期1500-1507,共8页Chinese Journal of Computers

基　　金：国家自然科学基金(61073049);上海市重点学科建设项目(J50103);教育部博士点建设基金(20093108110016)资助~~

摘　　要：文中对可重构三值光学处理器的原理和基本结构进行了详细的实验研究,证明了这种处理器的可重构性和重构电路的有效性.本次研究设计了实用的重构电路,使用小规模FPGA芯片、笔段式液晶显示器和高速光强传感器等元件,成功构造了一个像素位的可重构三值光学处理器.在实现的实验系统上,通过精心选择的50个实验用例,对三值光学处理器的全部42个基元和28个代表性逻辑运算器进行了研究.50个实验用例覆盖了所有可能的输入状态和各种基元组合情况.该文是对降值设计理论的第一次全面实践,为可重构三值光学处理器从理论到实际应用提供了实验基础和技术支持.In this paper, an experimental research about the principle and basic structure of Reconfigurable Ternary Optical Processor （RTOP） is proposed. The experimental results prove that the RTOP theory is valid and relevant reconfiguration circuitry works effectively. A practical reconfiguration circuitry was designed, and 1-pixel bit RTOP was made of a small-scale FPGA chip, some stroke segment liquid crystal screens, and some high-speed light density sensors. 50 elaborately chosen test cases were conducted on this experimental platform, which include all the 42 basic operation units （BOUs） and 28 typical logic operators, and cover all the combinations of input values as well as all the combinations of the different BOU types. As the first comprehensive implementation of decrease-radix design theory, this work lays experimental foundations and provides technical supports for the RTOP.

关 键 词：三值光学处理器 降值设计理论 基元 可重构 重构电路 实验 

分 类 号：TP38[自动化与计算机技术—计算机系统结构]