硅纳米晶存储器的耐受性研究  

Endurance Research on the Silicon Nano-Crystal Memory

作　　者：姜丹丹[1,2] 霍宗亮[2] 靳磊[2] 杨潇楠[2] 王永[2] 刘明[2] 

机构地区：[1]成都信息工程学院通信工程学院,成都610225 [2]中国科学院微电子研究所,北京100029

出　　处：《微纳电子技术》2014年第8期481-488,共8页Micronanoelectronic Technology

基　　金：国家重点基础研究发展计划(973计划)资助项目(2010CB934200;2011CBA00600);国家自然科学基金资助项目(61176073;61221004;61306107);中国博士后科学基金面上资助项目(2014M550866);成都信息工程学院科研基金资助项目(KYTZ201318)

摘　　要：首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。The preparation technology of the silicon nano-crystal and the basic characteristic of the silicon nano-crystal memory are introduced firstly. Then the physical mechanism of the silicon nano-erystal memory endurance degradation is discussed deeply. It is found that the interface trap induced by the stress is the dominant reason of the endurance degradation. Subsequently, the degradation mechanism of the interface trap is studied in detail with various analysis methods, such as the charge pumping method and CV curve analysis method. From the energy level distri- bution of the interface trap in the forbidden band, it is found that compared with the double-peak distribution of interface traps without the stress, the new P~,-type double-peak is generated after stressing. Finally, from the angles of the erase voltage reducing and carrier preheating, three new programming methods are proposed, and the endurance of silicon nano-crystal memory de- vices is effectively improved.

关 键 词：硅纳米晶存储器 耐受性 界面陷阱 能级分布 退化 

分 类 号：TB383[一般工业技术—材料科学与工程] TN304.12[电子电信—物理电子学]