基于FPGA的ARINC429总线IP核的设计与实现  

Design and Implementation of ARINC429 Bus Protocol IP Core Based on FPGA

作　　者：王琦[1] 张黎烁[2] 

机构地区：[1]河南财政税务高等专科学校现代教育技术中心,郑州451464 [2]河南工程学院计算机学院,郑州451191

出　　处：《河南师范大学学报（自然科学版）》2014年第4期149-153,共5页Journal of Henan Normal University(Natural Science Edition)

基　　金：国家自然科学基金(61175029)

摘　　要：为使计算机与ARINC429总线设备之间的数据通信更加方便,同时最大可能地降低设计成本.设计了ARINC429总线协议IP核,协议处理模块功能可以由可编程逻辑器件FPGA通过逻辑设计来实现,从而将总线的协议处理模块均集成于FPGA芯片上.在开发总线协议IP核时采用功能模块化方法,将逻辑设计划分为数据协议处理模块、缓冲模块、定时模块等部分.最后通过仿真验证,结果表明429总线协议IP核能够实现多通道数据的收发,逻辑设计符合ARINC429总线的数据传输要求,且满足特定场合的应用.In order to make the data communication between the computer and ARINC429 bus devices more easy and fast, and lessen the designing cost as low as possible, based on FPGA this article designs the ARINC429 bus protocol IP core. Protocol processing module was achieved by logic design in one FPGA chip. The integrated design and the operational principle of the IP core are given. With modular method, this design integrates the data protocol processing module, the data buffer module and timing module. Through simulation testing at last, the ARINC429 protocol IP core can achieve data transmission in multichannel and could meet the need of ARINC429 protocol character, and could be applied in series of situation.

关 键 词：FPGA ARINC429总线 IP核 收发模块 

分 类 号：V243.1[航空宇航科学与技术—飞行器设计]