基于SVA的FPGA接口时序验证方法研究  

A Timing Verification Method of FPGA Interface Based on SVA

作　　者：颜丽[1] 王伟[2] 黄莉雅[1] 

机构地区：[1]萍乡学院,江西萍乡337000 [2]九江职业技术学院,江西九江332007

出　　处：《萍乡高等专科学校学报》2014年第3期50-54,共5页Journal of Pingxiang College

摘　　要：本文介绍一种基于SVA(System Verilog Assertion)的FPGA接口时序验证实现方法,此方法以FPGA接口下级芯片的手册为基础,将手册中接口时序条件转换成SVA断言,并且在验证运行过程中,自动监测接口信号时序以到自动验证FPGA接口时序的目的。The paper gives an introduction to a timing verification method of FPGA interface based on SVA（System Verilog Assertion）. This method is based on the sheet of chip connected to the FPGA interface, and changing the timing conditions of interfaces in the sheet to SVA code. In the process of verification, interface signal is monitored automatically, and timing of FPGA interface is verified automatically.

关 键 词：FPGA 接口时序 SVA 

分 类 号：TN402[电子电信—微电子学与固体电子学]