12.5Gb/s 0.18μm CMOS时钟与数据恢复电路设计  

Design of 12.5Gb /s 0.18μm CMOS Clock and Data Recovery Circuit

作　　者：潘敏[1,2] 冯军[1] 杨婧[1] 杨林成[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096 [2]合肥工业大学计算机与信息学院,安徽合肥230001

出　　处：《电子学报》2014年第8期1630-1635,共6页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划(No.2011AA10305)

摘　　要：采用0.18μm CMOS工艺设计实现了一个12.5 Gb/s半速率时钟数据恢复电路(CDR)以及1:2分接器,该CDR及分接器是串行器/解串器(SerDes)接收机中的关键模块,为接收机系统提供6.25GHz的时钟及经二分接后速率降半的6.25Gb/s数据.该电路包括Bang-bang型鉴频鉴相器(PFD)、四级环形压控振荡器(VCO)、V/I转换器、低通滤波器(LPF)、1:2分接器等模块,其中PFD采用一种新型半速率的数据采样时钟型结构,能提高工作速率达到12.5 Gb/s.芯片测试结果显示,在1.8V的工作电压下,VCO中心频率在6.25GHz时,调谐范围约为1GHz;输入12Gb/s、长度为231-1的伪随机数据时,得到6GHz时钟的峰峰抖动为9.12ps,均方根(RMS)抖动为1.9ps;整个系统工作性能良好,二分接器输出数据眼图清晰,电路核心模块功耗为150mW,整体芯片面积0.476×0.538mm2.12.5 Gb/s half-rate clock and data recovery （CDR） circuit and 1：2 demultiplexer（DEMUX） applied to a serial- izer/deserializer （SerDes） receiver were designed and implemented in 0.18μm CMOS process. The CDR and DEMUX provided 6.25 GHz clock and 6.25 Gb/s data for the SerDes receiver. The circuit incorporated a Bang-bang phase/frequency detector （PFD）, a four-stage ring voltage-controlled oscillator （ VCO ）, a V/I （Voltage-to-Cun～nt） converter, a low pass filter （ LPF ）, a 1：2 DEMUX and so on. A new half-rate PFD which sampled the clock by data was adopted, and this PFD could increase operating rate up to 12.5 Gb/s.The tested results show that at the supply voltage of 1.8V, the tune range of VCO is about 1GHz at 6.25GHz centre frequency. When the data rate of the input pseudorandom is 12Gb/s and sequence length is 231 - 1 ,the recovered 6GHz clock has a root mean square （RMS） jitter of 1.9ps and a peak-to-peak jitter of 9.12ps.At the same time,the total chip can work well and the eye diagram of output data is clear. The die size is 0.476 × 0.538 mm2 and the core power consumption is only 150mW excluding the output buffers.

关 键 词：串行器/解串器(SerDes) 时钟数据恢复电路(CDR) 鉴频鉴相器(PFD) 压控振荡器(VCO) 

分 类 号：TN913[电子电信—通信与信息系统]