A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time  

作　　者：Yu Wang Zongliang Huo Huamin Cao Ting Li Jing Liu Liyang Pan Xing Zhang Yun Yang Shenfeng Qiu Hanming Wu Ming Liu 

机构地区：[1]Laboratory of Nano-fabrication and Novel Device Integration,Institute of Microelectronics,Chinese Academy of Sciences [2]Institute of Microelectronics,Tsinghua University [3]Institute of Microelectronics,Peking University [4]Semiconductor Manufacturing International Corporation

出　　处：《Chinese Science Bulletin》2014年第29期3935-3942,共8页

基　　金：supported in part by the Ministry of Science and Technology of China (2010CB934200,2011CBA00600);the National Natural Science Foundation of China (61176073);the National Science and Technology Major Project of China (2009ZX02023-005);the Director’s Fund of Institute of Microelectronics,Chinese Academy of Science

摘　　要：This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep submicron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. With the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-las/byte program speed and less than 50-ns read time under 3.3 V supply.

关 键 词：NOR闪存 访问时间 GB 浮栅 NS 深亚微米工艺 芯片电路 速度问题 

分 类 号：TN402[电子电信—微电子学与固体电子学]