基于资源复用的RSA加速器层次化架构  

Hierarchical architecture of RSA accelerator based on hardware resource reuse

作　　者：赵开兰[1] 张晓旭[1] 马德[2] 黄凯[1] 严晓浪[1] 

机构地区：[1]浙江大学电气工程学院,杭州310027 [2]杭州电子科技大学微电子CAD所,杭州310018

出　　处：《计算机工程与应用》2014年第19期78-84,共7页Computer Engineering and Applications

摘　　要：为了解决RSA在模频繁变化情况下性能不足的问题,在已有蒙哥马利模乘器的基础上采用层次化架构设计复用硬件资源,实现了基于改进扩展欧几里德算法的偶数模逆器和R2mod M运算器。实验结果显示,在14%的额外硬件资源开销下RSA加速器性能在模频繁变化应用下比原来提高2倍。其中,模逆器性能较其他设计提高了3倍,R2mod M运算器性能比复用模幂电路的实现方法提高了一个数量级。To improve the performance of the RSA cryptography system for the application of modular frequent change, a novel hierarchical architecture of RSA accelerator is proposed. With hardware resource reuse with Montgomery Modular Multiplier, both modular inverse and R2 mod M arithmetic function are supported by the proposed accelerator to improve performance of RSA key generation and Montgomery Modular multiplication. As the experiment shows, compared with previous works, the performance of RSA accelerator is 2 times faster for the application of modular frequent change under 14% resource overhead. What＇s more, the accelerator achieves one order of magnitude performance increasing for R2 mod M calculation comparing with the method of reusing Modular Exponentiation module.

关 键 词：RSA加密算法 加速 层次化设计 资源复用 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]