一种基于电容匹配算法的低噪声SAR ADC设计  

Design of a Low Noise SAR ADC Based on Capacitor Match Algorithm

作　　者：徐代果[1] 陈光炳[2] 刘涛[2] 

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路重点实验室,重庆400060

出　　处：《微电子学》2014年第5期573-577,共5页Microelectronics

摘　　要：设计了一个12位,采样速率为120kS/s的SAR ADC。提出了一种12位精度下,能在电容面积和精度之间进行折中的算法,使得电容的整体面积、速度和功耗达到优化。通过对比较器的设计,解决了在噪声环境下,影响比较器性能的电荷注入、带宽、转换速度等问题。在0.35μm2P5MCMOS工艺下进行了流片,测试结果表明,设计的SAR ADC的DNL和INL均小于±1LSB,功耗为1.5mW。A 12-bit 120 kS/s SAR ADC was designed with a trade off between the area and resolution of capacitor, and a special arithmetic for solving the contradiction was given to make the area, speed and consumption achieve a splendid level. A novel eomparator was implemented to overcome the offset, noise, charge injection, bandwidth and speed. Fabricated in 0.35 m 2PSM CMOS technology, the ADC consumed 1.5 mW, the DNL and INL were both less than ±1 LSB.

关 键 词：SAR ADC 电容匹配 低噪声比较器 

分 类 号：TN432[电子电信—微电子学与固体电子学]