电力线通信中LDPC译码器的优化设计与实现  

Optimized Decoder Design and Implement for LDPC Codes in Power Line Communications

作　　者：章谦骅[1] 章坚武[1] 

机构地区：[1]杭州电子科技大学通信工程学院,杭州310018

出　　处：《电测与仪表》2014年第20期105-108,共4页Electrical Measurement & Instrumentation

基　　金：国家自然科学基金资助项目(61001133;61102066)

摘　　要：电力线信道的噪声干扰很强,严重影响通信系统性能。文章提出了一种适于电力线通信中LDPC码的译码器硬件结构优化方法,并通过FPGA设计实现。算法的修正过程只包含简单的算术和逻辑运算,便于FPGA实现。本文方案提供的结构与常用的部分并行译码结构相比,节省了大量硬件资源。经软硬件仿真验证,硬件BP实现结构性能接近浮点BP算法,能应用于电力线通信等信噪比较低的传输领域。In a broadband low voltage power line channel,the interference from channel noise is heavy and results in a poor communication performance. This paper presents a optimization methods of the decoder of LDPC code for power line communication system,and implementation through FPGA. The correction process of this algorithm just includes simple arithmetic and logic operations,which is easy to be implemented by FPGA. Experiment has proved,compared with usual partial parallel decode structure,structure provided by this paper saves much hardware resources. Software and hardware simulations show that the proposed scheme approaches to the performance of a floating-point calcula-tion based the BP algorithm. Therefore,it can be widely used in power line communications and so on with low signal-to-noise ratio transmission.

关 键 词：电力线信道 LDPC码 FPGA 并行译码结构 BP算法 

分 类 号：TM73[电气工程—电力系统及自动化]