12位Sigma-Delta模数转换器的降采样滤波器设计  

Decimation Filter Design for 12-bit Sigma-Delta ADC

作　　者：黄博志 

机构地区：[1]福州瑞芯微电子有限公司,福州350003

出　　处：《电子与封装》2014年第10期25-29,共5页Electronics & Packaging

摘　　要：一种由SNR(信噪比)驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位SigmaDelta模数转换器的要求。The paper presents a signal-noise-ratio （SNR） based design method for the decimation filter of a 12-bit Sigma-Delta ADC （analog-to-digital converter）. Sigma-Delta ADC consists of Sigma-Delta modulatorand decimation filter. Sigma-Delta modulatoris used for signal modulation and over-sampling quantization. Decimation filter is used for down-sampling the digital signal to its normal frequency and the quantization noise is filtered at the same time. Sigma-Delta ADC has higher sampling frequency, higher precision and less hardware cost than traditional ADC. There are two specifications for decimation filter：down-sampling rate and filter performance. This filter design method is driven by SNR and two solutions are applied. Simulation is done using MATLAB and the result is met the requirement of 12-bit Sigma-Delta ADC with SNR larger than 74 dB.

关 键 词：信噪比 SIGMA-DELTA模数转换器 降采样滤波器 

分 类 号：TN402[电子电信—微电子学与固体电子学]