考虑硅衬底效应的基于TSV的3D-IC电源分配网络建模  

Modeling power distribution network in TSV-based 3D-IC with silicon substrate effect

作　　者：孙浩[1] 赵振宇[1] 刘欣[2] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073 [2]长沙学院数学与计算科学系,湖南长沙410003

出　　处：《计算机工程与科学》2014年第12期2339-2345,共7页Computer Engineering & Science

摘　　要：基于硅通孔TSV的3D-IC在电源分配网络PDN中引入了新的结构——TSV,另外,3D堆叠使得硅衬底效应成为不可忽略的因素,因此为3D-IC建立PDN模型必须要考虑TSV以及硅衬底效应。为基于TSV的3D-IC建立了一个考虑硅衬底效应的3DPDN模型,该模型由P/G TSV对模型和片上PDN模型组成。P/G TSV对模型是在已有模型基础上,引入bump和接触孔的RLGC集总模型而建立的,该模型可以更好地体现P/G TSV对的电学特性;片上PDN模型则是基于Pak J S提出的模型,通过共形映射法将硅衬底效应引入单元模块模型而建立的,该模型可以有效地反映硅衬底对PDN电学特性的影响。经实验表明,建立的3DPDN模型可以有效、快速地估算3D-IC PDN阻抗。Through Silicon Via （TSV） based Three-Dimensional Integrated Circuit （3D-IC） intro- duces TSV into Power Distribution Network （PDN）, and silicon substrate effect cannot be ignored be- cause of 3D stack. Therefore, modeling PDN in TSV-based 3DqC must take TSV and silicon substrate effect into consideration. A model for 3D PDN in TSV-based 3D-IC with silicon substrate effect is pro- posed. The proposed model is composed of a P/G （Power/Ground） TSV pair model and an on-chip PDN model. In the modeling procedure of 3D PDN, the P/G TSV pair model with a bump and a contact is proposed based on a proved model, which reflects the electronic characteristics of P/G TSV pairs better. Additionally, the on-chip PDN model, introducing the silicon substrate effect by conformal mapping method,is proposed based on the model proposed by Pak J S,which can reflect the silicon substrate effect on the electronic characteristics of PDN more effectively. The proposed model of 3D PDN is validated by experiments to prove that the proposed model of 3D PDN can evaluate the PDN impedance well and fast.

关 键 词：3D-IC 电源分配网络 P/G TSV PDN阻抗 硅衬底效应 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]