基于FPGA的异步FIFO的设计方案及性能  

Designs and Performance Study for Asynchronous FIFO Based on FPGA

作　　者：王齐双 黄震春[1] 蒲海峰 

机构地区：[1]清华大学计算机科学与技术系,北京100084 [2]中国兵器工业第203研究所,西安710065

出　　处：《弹箭与制导学报》2014年第6期185-189,共5页Journal of Projectiles,Rockets,Missiles and Guidance

摘　　要：分析了电子电路设计中异步FIFO设计的两个关键性难点:避免亚稳态现象的出现和空满状态的判断。为解决这两个问题,文中提出了四种方案:基于格雷码、基于移位码的、基于状态标志和基于区间地址的设计方案。设计方案均采用VHDL实现,并在FPGA的基础上进行仿真验证。结果显示这四种方案虽性能迥异,相差较大,但都有其独特的优势之处,能较好的完成异步FIFO的功能。Asynchronous FIFO has two key difficulties： metastable protection and identification of empty / full state. To solve these two difficulties,four solutions were proposed： the two are based on gray code and shift code,the other two are based on status flag and interval address. These four solutions were implemented with VHDL,and simulated on FPGA. The result shows that these four solutions all have their own advantages and can work well.

关 键 词：异步FIFO 亚稳态 二级同步链 格雷码 移位码 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]