基于RSIP核编译码器的设计与FPGA实现  

Design and FPGA Implementation of Reed-Solomon Coder / Decoder Based on IP Core

作　　者：郭勇 何军 

机构地区：[1]南京北方信息控制集团有限公司产品研发中心,江苏南京211153

出　　处：《无线电通信技术》2015年第1期90-93,共4页Radio Communications Technology

摘　　要：Altera公司的Reed-Solomon(RS)IP核功能强大,但使用该IP核需要进行握手信号的设计。介绍了一种基于IP核来实现RS编译码器的设计方法。分析了RS编译码器IP核握手信号的时序原理,并设计了相应的信号产生模块。介绍了RS IP核的参数配置和使用方法,并提供了整体的模块电路。为验证设计的正确性,对编译码器进行了时序仿真。针对具有最大误码的连续编码数据流进行纠错性能测试。时序仿真结果表明,该译码器能实现最大的纠错性能。The RS（ Reed-Solomon） IP Core from Altera Company is of great functions,but to use the IP Core,the design of the correlative alternation signal is necessary. The paper introduces a method of RS Coder / Decoder design based on the IP Core. The timing principle of the RS IP Core alternation signal is analyzed,and the corresponding signal-producing module of RS Coder / Decoder is designed. The method of parameter configuring and usage of the RS IP Core is also introduced,and the top – module diagram is provided. To validate the correctness of the design,the Coder / Decoder is simulated. To test the limit of its error-correcting performance,a continuous stream of coded symbols,which has the maximum error symbols,is simulated and tested. The test results of the timing simulation indicate that the RS decoder has the maximum error-correcting performance.

关 键 词：RS IP核 FPGA 文件读写 纠错性能验证 

分 类 号：TN911.12[电子电信—通信与信息系统]