2.5Gb/s PS/PI型半速率时钟数据恢复电路设计  

Design of a 2.5Gb/s PS/PI-Based Half-Rate Clock and Data Recovery Circuit

作　　者：李轩[1] 张长春[1] 李卫[1] 郭宇锋[1] 张翼[2] 方玉明[1] 

机构地区：[1]南京邮电大学电子科学与工程学院,南京210003 [2]南京邮电大学江苏省射频集成与微组装工程实验室,南京210003

出　　处：《微电子学》2014年第6期793-797,802,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61076073);中国博士后科学基金资助项目(2012M521126);江苏省自然科学基金资助项目(BK20130878;BK2012435;BK20141431);江苏省科技支撑计划-工业部分(BE2013130);教育部博士点基金资助项目(20133223120005;20133223110003);南京邮电大学基金资助项目(NY211016;BK20141431)

摘　　要：采用标准0.18μm CMOS工艺,设计了一种相位选择(PS)/相位插值(PI)型半速率时钟数据恢复电路。该电路主要由半速率Bang-Bang鉴相器、改进型PS/PI电路、数字滤波器和数字控制器等模块构成。改进型PS/PI电路通过两个相位选择器和两个相位插值器实现正交时钟的产生,相较于传统结构,减少了两个相位选择器,降低了复杂度和功耗。数字滤波器和数字控制器通过Verilog代码自动综合生成,降低了设计难度。Cadence仿真结果表明,输入2.5Gb/s伪随机数据时,电路在1.8μs时锁定,锁定后恢复出的时钟和数据峰峰值抖动分别为17.71ps和17.89ps,可以满足短距离I/O接口通信的需求。A half-rate clock and data recovery circuit based on Phase Selection（PS）/Phase Interpolation（PI） was designed in a standard 0. 18 μm CMOS process. The circuit mainly consisted of a half-rate bang-bang phase detector, a revised PS/PI circuit, a digital filter and a digital controller. The revised PS/PI generated two differential in-phase/quadrature clocks by means of two phase selectors and two phase interpolators. Compared to the traditional circuit, two phase selectors were eliminated, so its complexity and power were reduced. The digital filter and digital controller were automatically synthesized and realized by Verilog HDL modeling, so the design complexity was reduced. Cadence simulation results showed that with an PRBS input of 2.5Gb/s, the proposed circuit didn＇t lock until the time came to 1.8 μs, and the peak-to-peak jitters of the recovered clock and data were 17.71 ps and 17.89 ps respectively, which could meet the requirements of short-distance I/O interfaces.

关 键 词：时钟数据恢复 相位选择 相位插值 半速率 正交时钟产生 

分 类 号：TN432[电子电信—微电子学与固体电子学]