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出 处:《微电子学》2014年第6期829-832,共4页Microelectronics
基 金:国家自然科学基金重大项目(60990320;60990323);国家自然科学基金面上项目(61271090);国家高技术研究发展计划(863计划)重大项目(2012AA012305);四川省科技支撑计划项目(2012GZ0101)
摘 要:对一款75V功率场效应管失效芯片进行了分析。通过TCAD软件进行数值仿真,验证失效原因。在终端长度不变的前提下,获得具有两个场限环的终端结构,基本满足电场可靠性小于2.5×105 V/cm的要求。设计了三个场限环终端结构,击穿电压提高至94.7V,硅表面最大电场为2.17×105 V/cm,小于临界电场2.2×105 V/cm,降低了最大碰撞电离率,提高了器件的可靠性。Failure analysis of a 75 V power MOSFET chip was presented. The chip was tested and verified through two-dimensional numerical simulation. Keeping the termination length, 2 FLRs (Field Limit Ring) termination structure had been optimized to meet the basic electric field requirement of less than 2.5 × l0s V/cm. After further optimization, 3 FLRs termination structure had been designed, whose breakdown voltage was up to 94.7 V and maximum electric field at surface was down to 2.17 × 10^5 V/cm which was less than the critical electric field of 2. 2 × 10^5 V/era. The maximum impact ionization was also reduced . As a result, the reliability was improved effectively.
关 键 词:功率场效应管 失效分析 表面电场 碰撞电离率 可靠性
分 类 号:TN386[电子电信—物理电子学]
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