高压功率VDMOS元胞的研制  

Development of the cell of high voltage power VDMOS

作　　者：干红林 冯全源[1] 王丹[1] 

机构地区：[1]西南交通大学微电子研究所,四川成都610031

出　　处：《电子元件与材料》2015年第2期47-49,61,共4页Electronic Components And Materials

基　　金：国家自然科学基金资助项目(No.61271090);国家高技术研究发展计划(863计划)重大项目资助(No.2012AA012305)

摘　　要：基于Sentaurus TCAD仿真软件,在外延层参数与生产工艺确定的情况下,通过调整元胞的多晶硅长度优化特征导通电阻,并通过对版图元胞面积的准确计算,设计了三款导通电阻目标值为2.4,3.0和3.3Ω的高压功率VDMOS芯片。流片结果显示,导通电阻的平均值与版图计算值吻合度均超过96%,表明了该设计方法、仿真参数及版图设计具有较高的可靠性。Based on Sentaurus TCAD simulation software, under the situation of certained epitaxial layer parameters and production process, the specific on-resistance （Ron,sp） was optimized by the way of modulating the poly silicon length of the cell. And according to precise calculations about the cell area of layout, three high voltage power VDMOS chips with different Ron target values：2.4, 3.0 and 3.3Ω, were designed. The tape-out results show that the average Ron values fit the layout calculation values more than 96%, which performs that design methods, simulation parameters and the layout design possess high reliability.

关 键 词：功率器件 垂直双扩散场效应管 元胞设计 导通电阻 版图 流片 

分 类 号：TN386[电子电信—物理电子学]