基于内存地址映射的并行交织器的改进算法  

Improved Algorithm for Parallel Interleavers Based on Memory Address Remapping

作　　者：徐可[1] 茹国宝[1] 甘良才[1] 

机构地区：[1]武汉大学电子信息学院,武汉430072

出　　处：《科学技术与工程》2015年第3期240-243,共4页Science Technology and Engineering

基　　金：国家自然科学基金(61072041)资助

摘　　要：为了使具有高吞吐量特性的并行Turbo码译码得到应用,提出了并行无冲突交织器的数学模型,并由它得到一种改进的内存地址映射(IMM)方案,此方案能快捷高效地将传统的交织器变为并行交织器。仿真结果表明,相比传统的内存地址映射(MM)方案和优化的内存地址映射(OPMM)方案,IMM方案更加快速高效。在执行效率方面,IMM的效率比MM和OPMM分别提高了约96%和16%;在延时方面,IMM的延时比MM和OPMM分别降低至1/129和1/10。For the application of parallel turbo decoding with high throughput performance,a mathematical model for parallel collision-free interleavers was proposed,using which it develops an improved memory address remapping（ IMM） scheme that can convert a classic interleaver to a parallel interleaver readily and efficiently.As is shown in the simulation results,compared with the traditional memory address remapping（ MM） scheme and the optimized memory address remapping（ OPMM） scheme,IMM scheme is more quick and efficient.In the aspect of execution efficiency,the efficiency of IMM is about 96% and 16% higher,respectively than those of MM and OPMM;in terms of time delay,the time delay of IMM is about 129 and 10 times lower,respectively than those of MM and OPMM.

关 键 词：并行交织器 无冲突 内存地址映射 TURBO码译码 

分 类 号：TN911.22[电子电信—通信与信息系统]