带DLL反馈的延迟内插法TDC在FPGA上的实现  

A Tapped-Delay-Line TDC with DLL Feedback Implemented on FPGA

作　　者：邵琦[1] 周灏[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2015年第1期79-84,共6页Journal of Fudan University：Natural Science

基　　金：国家高技术研究发展计划资助项目(2012AA012001)

摘　　要：本文设计了在FPGA上实现的一款带全数字的延时锁定环（DLL）反馈的TDC电路,该TDC采用了延迟内插法延迟链结构.解决了利用FPGA配置电路对FPGA内部开关参数进行高低温（-55-125℃）测试的问题.延迟链选择的是FPGA中快速进位链,在0.18μm工艺FPGA上,分辨率在25℃下能达到167 ps.与另外一种在反熔丝结构FPGA上实现的TDC相比,分辨率在0℃,25℃,50℃分别提高了16.8％,16.5％,16.7％.在相同温度下,分辨率的变化基本保持一致,但反熔丝FPGA上的TDC需要对编码链进行反复的调整,而本文的TDC通过DLL锁定就可以完成对延迟链的调整,大大减小了开发和设计的时间和成本.Abstract： A single tapped-delay-line TDC with digital DLL based on FPGA is presented. It solves the problem of using FPGA configuration circuit to test inner switch parameters of FPGA in low and high temperature（ -- 55-- 125 ℃ ）. The dedicated fast carry line in FPGA is chosen. The resolution can achieve 167 ps in the temperature of 25 ℃ based on a process of 0. 18 μm FPGA. Compared to a TDK; implemented on an Anti-fuse FPGA, this circuil＇s resolution improves 16. 8%, 16. 5%, 16. 7% in the temperature of 0 ℃, 25 ℃, 50 ℃ respectively. The variations of resolutions are almost the same based on the same variation of temperature. The coding line of TDC in Anti-fuse FPGA requires many redesigns however the TDC in this paper adjusts its delay line by DLL feedback which may reduce the cost and time in the process of design and develop greatly.

关 键 词：现场可编程门阵列 时间数字转换 延迟内插法 数字延时锁定环 

分 类 号：TN432[电子电信—微电子学与固体电子学]