65nm FPGA中基于位宽选择的高速Block RAM设计  

The Design of 65nm FPGA's High-Speed Block RAM with Configurable Data Width

作　　者：陈丹[1] 王健[1] 张昕睿[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2015年第1期85-90,97,共7页Journal of Fudan University：Natural Science

基　　金：国家高技术研究发展计划资助项目(2012AA012001)

摘　　要：针对高性能现场可编程门阵列(FPGA)应用中数据存储交换的高速、多种位宽配置需求,本文设计了一种基于数据位宽可调整的高速Block RAM,并将其嵌入自主研发的FPGA芯片中.在该FDP15芯片中,Block RAM采用65nm的1P10M层金属,核电压1.2VCMOS工艺技术,可以实现1bit×16k,2bits×8k,4bits×4k不带校验位和9bits×2k,18bits×1k,36bits×512带有校验位的6种位宽选择模式,3种写入模式的双端口独立工作.文中针对位宽配置选择功能提出了一种单元可重复的电路结构,同时采用模拟位线延迟反馈机制实现了Block RAM较高的工作频率.流片测试的结果表明Block RAM可以实现真正的双端口独立工作,其6种位宽模式和3种写入模式功能正确,开关参数延迟可以达到2.25ns,与Xilinx同等功能、规模的芯片Virtex-4中内嵌Block RAM相比,性能接近.Abstract： In order to get a high-speed, multiple bit allocation of data storage and exchange in the high performance FPGA application, a design of Block RAM with eonfigurable data width is proposed and embedded in the FPGA chip developed by Fudan University. Our FDP15 FPGA chip is implemented in 65 nm IP10M 1. 2 V CMOS process, and embedded RAM can be configured to operate with a data width for 1 bit, 2 bits, 4 bits, 9 bits, 18 bits and 36 bits corresponding with an address space for 16k, 8k, 4k, 2k, lk, 512 data words. According to the function of bit allocation, a circuit structure which the unit can be repeated is proposed. Meanwhile the timing control design circuit using dynamic feedback ideology can optimize clock latency to get a higher frequency. The test results show that Block RAM in FDP15 has no fault and the function of reconfiguration work correctly, the achieved speed of this Block RAM can get the level of Xilinx Virtex4 with a pretty good DC and Switching characteristics （2. 25 ns）.

关 键 词：现场可编程门阵列 块随机存储器 位宽可配置 延迟反馈 

分 类 号：TN432[电子电信—微电子学与固体电子学]