基于FPGA的CRC校验算法的实现  

The Implementation of CRC Algorithm Based on FPGA

作　　者：张焱[1] 任勇峰[1] 齐蕾[1] 姚宗[1] 

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《电子器件》2015年第1期222-226,共5页Chinese Journal of Electron Devices

摘　　要：由于FPGA具有速度快、效率高、灵活稳定、集成度高等优点,所以在串行通信中采用FPGA来实现串口通信是十分必要的。由于通信传输的不确定性以及干扰等原因,串行通信经常会出现异常情况[1]。因此,在串行通信中添加CRC校验,可大幅度提高通信的可靠性。在论述了CRC校验原理的基础上,提出了硬件实现原理,并用VHDL硬件描述语言实现CRC校验,验证了方案的可行性。As FPGA is high speed,high efficiency,flexible and stable,high integration,etc.,so the use of FPGA in serial communications to achieve serial communication is essential. Due to the uncertainty in communication transmission and interference,serial communication often appears abnormal situation. Thus,adding the CRC in serial communication,can greatly improve the reliability of communication. On the basis of the discussion about the principles of the CRC,we present with the principle of hardware achievement and uses VHDL hardware description language to achieve CRC check,to verify the feasibility of the program.

关 键 词：电子 FPGA CRC校验 串行通信 VHDL 

分 类 号：TN919.3[电子电信—通信与信息系统]