基于CPLD的DSP与CAN控制器的接口设计与实现  

Design and realization of interface between DSP and CAN bus controller based on CPLD

作　　者：冯源 豆海利[2] 闫海明 

机构地区：[1]中国航空计算技术研究所,陕西西安710119 [2]空军工程大学理学院,陕西西安710051

出　　处：《现代电子技术》2015年第8期66-69,共4页Modern Electronics Technique

基　　金：航空基金(20111931001)

摘　　要：目前DSP处理器和CAN总线都在控制领域得到了广泛应用,在此以TMS320F2812 DSP处理器和独立的CAN控制器SJA1000为例,在分析DSP和SJA1000接口时序的基础上,采用CPLD有效地实现了两者之间数据和地址总线复用与非复用之间的转换和时序匹配。同时希望对于其他微处理器与CAN控制器的接口电路设计可以提供一定的参考。At present,digital signal processors （DSP） and CAN bus are applied widely to the control field. Taking the DSP TMS320F2812 and CAN controller SJA1000 as examples,the complex programmable logic device（CPLD）is used to realize the timing sequence matching effectively between data of DSP and SJA1000,and conversion of address multiplex bus and nonmultiplex bus based on the analysis of the interface timing sequence of DSP and SJA1000. It is hoped that it can provide a reference for the design of interface circuit between other microprocessors and SJA1000 CAN controller.

关 键 词：DSP CAN CPLD VHDL 哈佛结构 

分 类 号：TN710-34[电子电信—电路与系统] TP302.2[自动化与计算机技术—计算机系统结构]