一种基于自偏置技术的低功耗锁相环设计  

Design of a Low Power PLL Based on Self-Biased Techniques

作　　者：范昊[1] 黄鲁[1] 胡腾飞[1] 

机构地区：[1]中国科学技术大学电子科学与技术系,合肥230027

出　　处：《微电子学》2015年第2期196-199,共4页Microelectronics

基　　金：国家科技重大专项资助项目(2011ZX03004-002-01)

摘　　要：采用TSMC 0.13μm CMOS工艺,设计并实现了一种低功耗、具有固定的环路带宽与工作频率之比,以及良好相位噪声性能的自偏置锁相环（PLL）芯片电路。仿真结果表明,该PLL电路工作频率范围为200~800 MHz,在480MHz输出频率的相位噪声为-108dBc@1 MHz,1.2V电源供电下消耗功耗2mW。芯片核心电路面积仅为0.15mm2,非常适合应用于系统集成。A self-biased PLL circuit with low power consumption,fixed ratio of bandwidth to operating frequency,and good phase noise performance was designed and realized in TSMC 0.13μm CMOS process.Simulation results showed that the phase noise was-108 dBc @1 MHz at 480 MHz output frequency at the frequency range from 200 MHz to 800 MHz,and the power consumption was 2mW with 1.2Vpower supply.The area of the chip was 0.15mm2,which was suitable for system integration.

关 键 词：锁相环 自偏置 电荷泵 压控振荡器 

分 类 号：TN432[电子电信—微电子学与固体电子学]