一种改进的40Gb/s以太网循环冗余校验方法及电路设计  

An Improved Approach for Cyclic-Redundant-Code Generation and Circuit Implementation for 40 Gb/s Ethernet

作　　者：陈小莹[1] 于宗光[1,2] 雷淑岚[2] 周昱[2] 印琴 庞立鹏[2] 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2015年第2期245-248,257,共5页Microelectronics

基　　金：江苏省"333"工程科研项目资助(BRA2011115)

摘　　要：针对在40Gb/s以太网规范中定义的循环冗余校验码(Cyclic Redundancy Code,CRC)计算关键路径过长的问题,提出了一种分块处理的方法来缩短每条关键路径的计算时间,从而满足时序的要求。对电路进行仿真,并使用中芯国际65nm工艺库进行综合。验证结果表明,提出的分块并行计算方法正确,并且能够提高CRC计算速度,满足时序要求。Because the cyclic redundancy code defined in a 40Gb/s Ethernet specification had a long critical path to calculate,a method to increase the speed of CRC-32 based calculation was put forward.The circuit was simulated,and it was synthesized targeting SMIC 65 nm process by using Design Compiler.The synthesis results showed that the proposed method was correct.It could increase the speed of CRC generation and was highly applicable in ultra high-speed circuit design.

关 键 词：40Gb/s以太网 CRC-32 数据分块 综合 

分 类 号：TN402[电子电信—微电子学与固体电子学]