针对智能卡的可重构SHA-3模块设计及FPGA实现  

The Design and FPGA Implement of the Reconfigurable SHA-3 module for smart card

作　　者：高建新[1] 崔建明[2] 张小军[1] 韩燕丽[2] 

机构地区：[1]山东科技大学电子通信与物理学院,山东青岛266590 [2]山东科技大学信息科学与工程学院,山东青岛266590

出　　处：《中国集成电路》2015年第4期38-41,共4页China lntegrated Circuit

摘　　要：SHA-3凭借高安全性及易硬件实现等优点被广泛应用在信息安全领域。但在目前应用中,其硬件输出长度固定,支持的模式较少,无法满足不同场合需求。针对该缺点,本文设计一种高性能可重构的SHA-3模块,可支持4种不同参数。同时通过分析SHA-3在智能卡芯片中的应用特点,提出一种针对运算固定且计算方式较少的硬件加速方法。该方法通过在进行SHA-3多轮迭代的时间并行运行其他计算,减少CPU与SHA-3模块数据带宽和处理时间。FPGA实验表明:该设计在Xilinx xc3s5000上可实现时钟频率最高246.49MHz,占用3593slices,吞吐量可达4710Mbps。SHA-3 algorithm is widely used in the field of information security because of high security and hardware implementation easily. But in the current application, the output of hardware has fixed length, little support models, that cannot meet the demand for different occasions. Against the disadvantages, we design a SHA-3 algorithm module which has high performance and can be reconfigure, it can choose 4 models freely. And we propose a method of hardware acceleration which be designed for the feature of fixed for operation and less calculation by analyzing the application feature of the SHA-3 algorithm in smart card chip. This design reduces the CPU and SHA-3 algorithm module communication data quantity and time by utilizing SHA-3 algorithm rounds of iteration to other parallel computing The FPGA experiment show that the design in Xilinx xc3s5000 achieve highest clock frequency 246.49 MHz, takes up 3593 slices, throughput can be up to 4710Mbps.

关 键 词：SHA-3 海绵结构 可重构 硬件加速 FPGA 

分 类 号：TN791[电子电信—电路与系统]