薄层SOI场pLDMOS击穿机理研究  

Breakdown mechanisms of thin layer SOI field pLDMOS

作　　者：邓晓燕 李庆 李娟 刘磊 

机构地区：[1]中国武警警官学院电子技术系,四川成都610213

出　　处：《重庆邮电大学学报（自然科学版）》2015年第2期219-223,共5页Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)

摘　　要：为了解决薄层SOI(silicon-on-insulator)场LDMOS(laterally diffused metal oxide semiconductor)击穿电压偏低,容易发生背栅穿通的问题,提出一种基于场注入技术的薄层SOI场pLDMOS(p-channel lateral double-diffused MOSFET)。通过建立该场pLDMOS的穿通机制数学模型,分析了其4种击穿机理:背栅穿通、沟道横向穿通、横向雪崩击穿和纵向雪崩击穿。仿真结果表明,场注入技术穿过厚场氧层向下注入硼杂质,通过控制注入能量和体区浓度获得浅结深,从而提高器件对背栅穿通的抵抗力;优化的沟道长度和埋氧层厚度分别消除了沟道的横向穿通和纵向雪崩击穿;双层场板结构调制器件表面电场分布,避免了器件过早地横向雪崩击穿。在优化器件相关结构参数和工艺参数基础上,成功基于1.5μm厚顶层硅SOI材料研制出耐压300 V的场pLDMOS。相比较于常规厚层场pLDMOS器件,顶层硅厚度由大于5μm减小到1.5μm。A field p-channel lateral double-diffused MOSFET（ pLDMOS） based on thin layer SOI is presented in this work. Field implant（ FI） technology is developed to prevent back gate punch-through and improve the toleration capability of breakdown voltage for thin layer SOI field pLDMOS. Mathematic models accounting for the punch-through mechanisms of field pLDMOS are set up. Breakdown mechanisms of back gate punch-through,lateral channel punch-through,vertical and lateral avalanche breakdown are investigated by simulating related parameters and experimental verification. Optimization of the device structure is done based on above researches. Shallow junction achieved through proposed FI technology with advisable FI energy and Nn-wellattenuates back gate（ BG） effect; advisable thickness of buried oxide dispels vertical avalanche breakdown and field plate technology avoids premature lateral avalanche breakdown by modulating electric field distribution; optimized channel length eliminates lateral channel punch-through. Finally,the 300-V field pLDMOS is implemented experimentally on 1. 5-μm-thick SOI layer. Compared with the conventional thick layer SOI field pLDMOS,the thickness of SOI layer is reduced from above 5 μm to 1. 5 μm.

关 键 词：薄层SOI 场pLDMOS 场注入技术 背栅效应 击穿机理 

分 类 号：TN386[电子电信—物理电子学]