检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
机构地区:[1]北京交通大学电子信息工程学院,北京100044
出 处:《北京交通大学学报》2015年第2期100-105,共6页JOURNAL OF BEIJING JIAOTONG UNIVERSITY
摘 要:为了解决传统的非制冷红外焦平面(IRFPA)读出电路(ROIC)分辨率单一的问题,设计了读出电路的数字控制时序电路,基于可综合Verilog HDL(Hardware Description Language,硬件描述语言)设计了控制积分器复位、采样/保持器状态转换和行列选通的时序电路,通过窗口选择实现256×256到128×128分辨率的转换.采用SMIC 0.18μm CMOS工艺,进行DC综合和布局布线等,最终生成版图.并在Modelsim下进行了前仿与后仿,仿真结果表明:整个设计能够实现预期的分辨率可调功能,达到IRFPA多窗口读出的要求和细节捕捉的目的.A time control module for uncooled Infrared Focal Plane Array(IRFPA) Readout Integrated Circuit(ROIC) is proposed to solve the problem of single resolution in traditional design. Based on syn- thesizable Verilog HDL, this module can realize several functions including controlling the integral time, the sampling states and selecting switch of row and column. The variable resolution is imple- mented by window selection, which can be transformed from 256 × 256 to 128 × 128. The layout is generated based on SMIC 0.18 μm CMOS technology after a series of operations such as logic synthe- sis, plaing and routing, etc. This design is compiled and simulated with Modelsim including pre-simu- lation and post-simulation. Simulation results show that this design can realize the variable resolution in order to capture the details and satisfy the requirements of various IRFPA ROICs as well.
关 键 词:读出电路 非制冷红外焦平面阵列 时序控制 分辨率可调 VERILOG HDL
分 类 号:TN402[电子电信—微电子学与固体电子学]
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.33